In 2019, in a small restaurant in Paris, a man set a laptop on a dinner table for two other engineers to examine. What was on it should not have existed. They were looking at a Process Design Kit, or PDK: the complete set of physical rules and transistor models used by a chip factory in the United States to manufacture silicon. These documents were among the most fiercely guarded in the global technology industry; no engineer outside the factory’s customer roster could see one without first signing a non-disclosure agreement (NDA). The fact that it was on a laptop in Paris, with no NDA attached, was the start of something.

Seven years later, that beginning has become a small constellation of open silicon projects. Together, they enable the design and manufacture of working chips with software anyone can read, modify, and share.

European Union public money has paid for a meaningful part of what now exists, and most Europeans have no idea. To see why it matters, you have to understand what designing a chip actually entails, and why almost none of that process was open before 2019.

How Chips Get Designed: EDA

Picture the work that ends in producing a microchip as a tall stack of software. At the top, humans sit at keyboards writing in hardware description languages such as SystemVerilog. Their code describes what the chip should do in terms of logic, not yet as physical shapes. Beneath that human-readable layer, a pile of automated tools translates the logic downward: Synthesis turns the description into gates, placement and routing decide where those gates sit on the silicon surface of the chip, verification checks the design against its specification, and sign-off tools confirm that the design meets the manufacturing rules and standards of the chip factory — called a “foundry” in the industry. At the bottom of the stack, the foundry uses finished designs to produce physical chips.

The stack of tools between the engineer and the foundry is all part of the category “Electronic Design Automation,” or EDA. Most chip designers work “fabless,” meaning they design entirely on their computers, send their finished files to a foundry that builds the chips, and the foundry ships the chips back. The whole supply chain is software-mediated, and most of that software comes from just three companies: Cadence, Synopsys, and Siemens EDA. Together, they control the bulk of the market — by most estimates, 75 to 90 percent.

The pricing of these tools is not public. People in the industry quote licensing fees in the million-euro range per engineer per year, with case-by-case custom discounts of 99 percent or more. That opacity is a kind of leverage: A vendor who decides who gets how big a discount also decides which customers, which sectors, and which countries can afford to participate. It is geopolitical influence dressed up as commercial pricing.

There is one more piece. When an engineer has finished with their chosen toolchain (top to bottom, logic to layout), foundries require a final check using a proprietary sign-off tool such as Siemens’s Calibre before manufacturing begins. The open ecosystem has to interoperate with that gate; nobody can replace it without the foundry’s blessing.

The Chokepoint: PDK

For most of the industry’s history, almost none of the chip production software stack could practically be opened — and not because nobody tried. The bottom layer, the foundry, kept the most important document a designer needed locked up: the Process Design Kit, or PDK.

A PDK is the bundle of files — transistor models, design rules, library cells, parameters — that a foundry hands its customers so their tools can produce designs the foundry can actually manufacture. Every foundry has its own PDK for each process it offers. Until 2019, all the commercially relevant PDKs in the world were under license and NDA.

Luca Alloatti, a silicon photonics researcher and one of the co-founders of the Free Silicon Foundation (F-Si), gave an analogy to help envision this situation. Imagine that Microsoft Word didn’t have just one .docx format, but also .docx1, .docx2, .docx3, all the way through to .docx1000000, and each of those formats were individually under NDA. LibreOffice, in this world, would still want to read them. But if any LibreOffice contributor had ever signed an NDA on any .docx version and a parser for that version then appeared in the LibreOffice source tree, Microsoft could sue the whole project. Functionally, the entire ecosystem of free office software compatible with proprietary formats could not exist.

That is roughly the situation that produced closed EDA. A researcher’s fix to make a free tool work with one foundry’s PDK would live and die on their machine. There was no way for a public, compounding body of knowledge to form. Even when open chip-design tools such as the DARPA-funded project OpenROAD (started under Andrew B. Kahng at the University of California, San Diego) did connect to a real foundry after going through closed-PDK gymnastics, nobody could share those routines with other engineers.

Open source software cannot exist without a through line of openness: If your open code has to talk to secret code to function, you cannot legally publish it. The industry had arranged itself, for decades, to keep the fabrication layer secret.

The Unlock: The Paris Laptop

The man with the laptop in Paris was Jeff Carr, one of the co-founders of DigitalOcean, a US cloud computing company. Sometime around 2018, he became personally interested in the open silicon question. He drove out to a foundry called SkyWater Technology, parked outside, and walked in to ask how much it would cost to buy the factory. He did not buy it. But through some combination of his involvement and a push from Google, the SkyWater 130-nanometer PDK emerged: the first open Process Design Kit in the world.

The laptop in Paris a year later linked up the full EDA stack, from node (industry shorthand for a particular manufacturing process and its physical scale) to tapeout (the moment a finalized design is committed to a foundry for commercial production). A real foundry and a real manufacturing process, available to anyone, without any NDAs.

What followed Paris was a cascade. GlobalFoundries, a much larger US foundry, opened its GF180MCU process (a 180-nanometer node aimed at microcontrollers) in partnership with Google. Then came IHP Microelectronics in Germany, the country’s national research foundry. OpenROAD’s five-and-a-half-year DARPA program concluded at the end of 2023; the project has continued as a nonprofit, with paid commercial support offered through Precision Innovations. Since 2019, several hundred chips have been taped out using open tools. Google’s open shuttle program alone has manufactured 360 designs, selected from more than 600 submissions across 19 countries.

In a “130-nanometer node,” the smallest features are roughly 130 nanometers across. The cutting edge today is 3 nanometers and below, dominated by TSMC, the Taiwanese foundry that fabricates the world’s most advanced chips. Open silicon is not competing at that frontier, but at mature nodes (130nm, 180nm, 90nm) where the bulk of real-world chip applications live: in automotive sensors, analog circuits, microcontrollers, home appliances, anything that does not need to push silicon to its physical limits. OpenROAD, the open source digital design tool, has been used for commercial tapeouts at nodes from 180 down to 12 nanometers.

Seven years ago, you could design openly but not fabricate openly. Today, open silicon projects have users whose work, built end-to-end with open tools, has reached industrial tapeout to produce chips at scale.