Exploring the RISC-V processor architecture

New Chip in Town

© Photo by Jason Jarrach on Unsplash

© Photo by Jason Jarrach on Unsplash

Article from Issue 256/2022
Author(s): , Author(s):

The open source RISC-V processor architecture is poised to shake up the processor industry. Thanks to the Qemu emulator, you can get to know the RISC-V without waiting for affordable hardware.

Most of the IT industry has consolidated around Intel-equivalent processors with the x86 and (related) AMD64 architectures. But just two decades ago, several other processor manufacturers and architectures were fighting for a place in the market. Many of these processors (including MIPS, PowerPC, Alpha, and SPARC) followed a set of principles for processor design known as Reduced Instruction Set Computer (RISC). RISC systems live on today, most notably in the ARM architecture used in today's in smartphones, Raspberry Pis, and other electronic devices. (The acronym ARM actually stands for Advanced RISC Machine.) But another RISC contender is also on the rise.

RISC-V, pronounced "Risk Five," is widely hailed as a shooting star in the processor architecture sky [1]. Proponents believe RISC-V can do everything ARM can do – and it is all open source and royalty free. The non-proprietary nature of RISC-V means it could allow small chip makers to get in a game that is now dominated by a few tech giants. And even mainstream vendors could one day gain an edge by choosing RISC-V and avoiding licensing fees.

At just 10 years old, the RISC-V architecture is still considered comparatively young. If you can live without Linux and prefer FreeRTOS, you can get started today and gain some RISC-V experience on reasonably priced hardware (see the box entitled "Hardware Options"). Until recently, if you were looking for a RISC-V processor capable of running Linux, you would have to pay as much as EUR600. As this issue goes to print, an affordable, Linux-ready RISC-V board has finally reached the market, though little is known about it [2].

Hardware Options

The ESP32-C3-DevKitC-02 board, which features a RISC-V core, is available in mail order shops for prices starting at around EUR10 (Figure 1). Chinese manufacturer Espressif has added a RISC-V-based ESP32-C3 to its well-known and successful ESP32 model; it has slightly slower performance than the classic model, but it is smaller and less expensive.

Figure 1: Espressif is already offering its ESP32-C3-DevKitC-02 RISC-V board for a low price.

If you want to get to know RISC-V in combination with Linux, you can do so right now without waiting for the perfect hardware. A RISC-V compiler is available for Ubuntu, and the Qemu hardware emulator is also available to emulate a complete 32- or 64-bit RISC-V system. Some Linux distros already have RISC-V variants of their software collections, so you can quickly get to work.

This article shows how to take your first steps with exploring Linux on RISC-V – but first a little background.

About RISC-V

Ten years ago, computer scientists at the University of California, Berkeley (UC Berkeley), developed a new CPU instruction set architecture (ISA) known as RISC-V (Figure 2); the idea was for RISC-V to be modern and suitable for both teaching and research, as well as actual applications [3]. The special highlight was the BSD-based licensing model, which allows the licensee to use the architecture free of charge (Table 1).

Figure 2: The RISC-V logo.

Table 1

RISC-V Features

Modularity

Basic Instruction Set Plus Extensions

Register width

32, 64, 128

No. of registers

16 (for embedded), 32, 64

Architecture type

Load/Store

File storage format

Little Endian

Number of instructions

40 (RV32I, Computational, Control Flow, Memory Access)

Privilege Levels

3

Machine type

Three register machine

Instruction types

6 (R, I, U, S, B, J)

Software

Comprehensive software ecosystem with popular software stacks (Linux, FreeRTOS)

Misc.

Stable specification, no further changes planned

Over the past few years, companies large and small have begun to explore the possibilities of RISC-V; developing, producing, and distributing hardware with a RISC-V core; and making their designs available free of charge. The large Chinese online retailer Alibaba, for example, has completely disclosed the RISC-V core it developed, as has disk manufacturer Western Digital. Even Apple, which has a very powerful and efficient ARM CPU up its sleeve in the form of its M1 chip, has recently been looking for RISC-V developers.

Much like ARM, but in total contrast to x86, the RISC-V architecture scales very well to small sizes. In addition to variants that have a full-blown memory management unit (MMU) and are therefore suitable for Linux, RISC-V supports very simple microcontrollers for bare-metal programming, which makes it suitable for programming that does not require system software or is equipped with the FreeRTOS real-time operating system.

The simplest RISC-V variants implement only the core instructions, also known as the I-instructions. In addition to logical operations, these core instructions consist of just adding and subtracting; multiplying and dividing are reserved for the M-extension. Table 2 lists examples of RISC-V extensions, such as the F extension for floating point or the C extension for compressed instructions. UC Berkeley suggests implementing at least the I, M, F, D, and A extensions and uses the letter G (for "general") to abbreviate this architecture to RV32G.

Table 2

A Selection of RISC-V Instruction Set Extensions

RV32I

Base Instruction Set

RV32A

A extension (atomic read-modify-write)

RV32B

B extension (bit manipulation)

RV32C

C extension (compressed instructions)

RV32D

D extension (double precision floating point)

RV32F

F extension (single precision floating point)

RV32M

M extension (multiplication, division)

RV32S

S extension (supervisor level instructions)

RV32V

V extension (vector instructions)

RISC-V is defined as a 32-, 64-, and even 128-bit architecture. In other words: All internal registers have a width of 32, 64, or even 128 bits, depending on the architecture. There are no less than 32 or 64 of these registers, which are numbered X0 to X31 or X63. Apart from the register X0, which can only be read and where all bits are set to 0, the registers can be used universally. For example, there is no special stack pointer. However, the architecture provides for a separate program counter (PC) (i.e., an instruction counter that contains the address of the instruction that the CPU needs to process next).

Whereas the x86 architecture is a two-register machine, RISC-V typically has three registers involved in an operation. If a two-register machine adds the contents of two registers, it has to store the results in one of the two registers. A three-register machine, on the other hand, can store the result in a third register (X1 = X2 + X3).

Installing RISC-V Linux

You can't just call apt install on Ubuntu to get started. In fact, for an emulated RISC-V machine, you need a BIOS, a bootloader, and finally, the Linux operating system itself.

This all starts with the RISC-V compiler, which you install by typing

apt install gcc-riscv64-linux-gnu

Download the latest version of the OpenSBI open source BIOS and generate the BIOS. The bootloader is U-Boot, which is well known in the embedded area – you will need to compile a RISC-V version of U-Boot.

The RISC-V server image [4] hosted by Canonical targets a small memory footprint at 466MB. You still need to convert this to a usable size after downloading and unpacking the image using the Qemu tools. Whether this size will be 20GB or just 5GB is something you'll need to decide for yourself.

Finally, you need to launch Qemu with a plethora of parameters, especially for the network connection, if you want to use Internet access. User Aaronfranke provides a script [5] that maps the essential installation steps. Listing 1 shows a variant that we modified and extended; the script optimizes, adjusts, and conjures up a bootable system more or less automatically.

Listing 1

RISC-V Ubuntu for Qemu

#!/bin/bash
BASISDIR=~/risc-v
UBUNTU_IMG=ubuntu-20.04.3-preinstalled-server-riscv64+unmatched.img
if test ! -f `type -p riscv64-linux-gnu-gcc`; then
  echo "install compiler..."
  sudo apt install gcc-riscv64-linux-gnu
fi
if test ! -f `type -p qemu-system-riscv64`; then
  echo "install qemu..."
  sudo apt install qemu-system-misc qemu-utils
fi
if test ! -d ${BASISDIR}; then
  echo "mkdir ${BASISDIR}"
  mkdir ${BASISDIR}
fi
cd ${BASISDIR}
if test ! -f opensbi/build/platform/generic/firmware/fw_payload.bin; then
  wget https://cdimage.ubuntu.com/releases/20.04/release/${UBUNTU_IMG}.xz
  xz -dk ${UBUNTU_IMG}.xz
  qemu-img resize -f raw ${UBUNTU_IMG} +6G
  export CROSS_COMPILE=riscv64-linux-gnu-
  git clone https://source.denx.de/u-boot/u-boot.git
  cd u-boot/
  git reset --hard v2021.10-rc3
  make qemu-riscv64_smode_defconfig
  make -j$(nproc)
  cd ..
  git clone https://github.com/riscv/opensbi.git
  cd opensbi/
  make PLATFORM=generic FW_PAYLOAD_PATH=../u-boot/u-boot.bin
  cd ..
fi
qemu-system-riscv64 -machine virt -m 4G -nographic \
  -bios opensbi/build/platform/generic/firmware/fw_payload.bin \
  -smp cores=2 -gdb tcp::1234 \
  -device virtio-net-device,netdev=eth0 \
  -netdev user,id=eth0,hostfwd=tcp::2222-:22 \
  -drive if=none,file=${UBUNTU_IMG},format=raw,id=mydisk \
  -device ich9-ahci,id=ahci -device ide-hd,drive=mydisk,bus=ahci.0 \
  -device virtio-rng-pci

The script creates a new risc-v/ subfolder in your home directory, installs the necessary software by running apt install, and reloads the other required components, including the pre-built Ubuntu image off the web. It generates the firmware and the bootloader and finally starts RISC-V Linux. Incidentally, the download and installation only occur on the first call.

Save the script in a file named, say, risc-v-linux.sh, change the access rights to execute by typing

chmod 755 risc-v-linux.sh

and finally start the installation. Launch Linux in the console by calling

./risc-v-linux.sh

At this point, however, you will need some patience, because the RISC-V CPU implementation in Qemu is a software emulation rather than virtualization. A few minutes later, however, you should be prompted to log in, and you can comply by entering the username ubuntu with the initial password of ubuntu (Figure 3). The system will then force you to change the password for security reasons.

Figure 3: The login screen for RISC-V Ubuntu.

No Command-Line Fun

Since the serial console has some weaknesses, it is best to log in to the new system via SSH using another terminal window. Qemu configured our script for SSH login, so you can type

ssh -p 2222 ubuntu@localhost

Now enter the uname -a command, and you will see that you are working on a RISC-V machine. cat /proc/cpuinfo also shows the architecture, including the implemented extensions, but is otherwise surprisingly terse. cat /proc/interrupts, dmesg, or file /usr/bin/bash show further traces of the RISC-V architecture (Figure 4). On the whole, however, Linux lives up to its reputation as a platform-independent operating system by carefully concealing the new CPU architecture under the hood.

Figure 4: Traces of the RISC-V architecture are easy to find.

Use apt update to update the package list in the usual way. But avoid apt upgrade, which could swap the kernel and bootloader and cause problems. Generally speaking, the software will not be one hundred percent stable across the board. Once you have installed a compiler and developer tools by typing

apt install build-essential gdb vim

you can enter and compile a small Hello RISC-V program. Then check out the CPU registers and assembler code in the GNU debugger (Figure 5).

Figure 5: Disassembling a small "Hello, RISC-V" program in the GNU debugger.

By the way, the CPU registers do not use the previously mentioned register designations X0 to X31 in the debugger or in the output of the dmesg --kernel command. Instead, you will see the names ra, sp, t0, s6, and so on. The RISC-V Foundation proposed – or specified – a convention for the use of the registers, and the programmers or the manufacturers of the development tools also adhere to this convention. According to the convention, for example, register X2 acts as a stack pointer (sp); X1 contains the return address (ra) for a subroutine call. Registers with a T in their names are used to cache data, and those that start with an A contain the call parameters when a function is called.

Developers don't have to worry about these details in most cases; they are mainly relevant for kernel programmers when debugging.

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