Open Hardware – RISC-V

The lack of open source computer chips has always been a major obstacle to the development of free hardware. The supply is limited, which can limit the number of open hardware units, and suppliers have been known to substitute proprietary chips without informing the manufacturer. In recent years, such problems have been alleviated by single-board microcontrollers, like those made by Arduino, but these devices are useful mainly for dedicated hardware with limited capacity. Now, however, the situation is on the verge of changing – in no small part because of the emergence of the RISC-V (pronounced "RISK Five") chip, which is starting to be used in proprietary and open hardware alike [1].

The idea of reduced instruction set computers, or RISC chips, has been around for several decades [2]. RISC refers to chips that have a greatly simplified set of instructions, which can make operations more efficient and reduce power expenditure. For example, rather than access to memory being included in most of the instructions that the chip uses, in a RISC chip, access to memory may be included only for operations in which it is needed. Examples of RISC-type architecture includes the PowerPC, MIPS, and SPARC, as well as the use of ARM in iOS and Android devices.

RISC-V is one of the latest implementations of the RISC concept. It originated in a three-month project in the summer of 2010 at the University of California, Berkeley, in their Electrical Engineering and Computer Sciences department's computer science division. Further development of the RISC-V architecture was funded by the Defense Advanced Research Projects Agency (DARPA), led by Krste Asanovic, Yunsup Lee, and Andrew Waterman. According to Jack Kang, the vice president of product and business development at SiFive [3], a company founded by the original developers, "the team was able to prove that smaller teams could design state-of-the-art silicon." The initial specifications were released under a BSD license, making the specifications an open standard that could be used for both proprietary and open purposes – a decision that played a major role in RISC-V's development, especially since no other chip specification was so accessible to users. The interest was immediate, and in 2015, the RISC-V Foundation was established: a non-profit organization that develops and promotes the RISC-V Instruction Set Architecture (ISA).

In the last three years, interest in RISC-V has been accelerating. Rick O'Connor, the executive director of the RISC-V Foundation describes RISC-V as attracting interest in research, academia, and industry alike. "The Foundation's membership exceeded 100 organizations in November 2017," O'Connor says. "That's a 120 percent membership growth since November 2016, featuring both established technology giants and emerging startups."

In fact, the interest in RISC-V is worldwide. The latest in the ongoing series of RISC-V Workshops was held in Barcelona in May 2018, and another is scheduled in Chennai, India, in July 2018. Additionally, talks about RISC-V are scheduled later this year for the IEEE International Symposium on High Performance Computing and the Design Automation Conference in San Francisco. Recently, too, SiFive raised $50.6 million in startup capital [4]. Clearly, RISC-V is a standard whose time is about to arrive.

The Advantages of RISC

Why is RISC-V of such interest? To start, as O'Connor notes, chip development has reached a state where the existing architectures can do little to increase performance. "New heterogeneous, purpose-built accelerators are required to deliver ever-increasing performance needs." To all appearances, RISC-V appears to deliver the new approach that is required for the chip industry to continue development.

In the RISC-V State of the Union in Barcelona in May 2018, Krste Asanovic summarized some of the advantages that RISC-V delivers [5]. First, as the name implies, RISC-V is a simpler and smaller instruction set than other existing ISAs. It features what Asanovic describes as a clean state design that clearly separates user and root privileges. Even more importantly, RISC-V's memory model is unique in the way that it takes different types of users into account. Early on, RISC-V made the decision to keep the core as stable as possible, whenever possible adding new features through extensions. As O'Connor says, the "ISA base and standard extensions are frozen and are not expected to change in any way except for clarifications and improvements in its documentation." The result is an architecture that is unique among ISAs.

This decision shows in the memory model, which includes sections for the ISA core, with another section reserved for future developments. Vendors can make use of the reserved section, but at the possible expense of breaking compatibility with future versions of the ISA – a hazard that may be acceptable for a one-off device or one with a short shelf life. However, vendors are encourage to place any proprietary code into a custom section of the memory. As O'Connor points out, this arrangement allows for "user extensibility without breaking existing sections or incurring software fragmentation" (Figure 1).

Figure 1: The RISC-V memory model includes reserved space for free-licensed core components and future common developments and custom space for proprietary extensions, which accommodates different types of users.

However, the licensing is of equal importance. Besides the BSD licensing of the original code, the RISC-V Foundation is also developing a permissive license suitable for the formal specifications. No doubt free software advocates would prefer a copyleft license like the GNU General Public License (GPL), which would require all derivative works to use a similar license. The trouble is, as chip designer Andreas Olofsson points out, "The semiconductor industry would not take kindly to a copyleft license like GPL, which would force a company to open up everything inside the chip. Permissive licenses like the MIT license and BSD enable large risk-averse companies (with legal departments) to participate. With permissive licenses, there is always the risk that big companies will only take (and not give back), but with GPL style licensing in [use] they just won't get involved" [6].

As things are, RISC-V in effect acts as an open standard rather than a formal license. "RISC-V is license-free and royalty-free," O'Connor says, "which means you can build custom processors with zero licensing cost. Our intent is to provide a long-lived open ISA with significant infrastructure support." This includes documentation, compiler tool chains, operating system ports, reference software simulators, architectural test suites, and teaching materials." Although proprietary companies can use these tools for their short-term advantage in bringing products to market, small open hardware manufacturers gain access to what until now has been difficult or impossible to obtain. While not ideal by free software standards, the trade-off is perhaps acceptable. As Asanovic says, for all users, RISC-V offers "minimum wasted work through maximum reuses" of resources.

Risk Management

If, as seems likely, RISC-V adoption continues at the current rate, for the first time, hobbyists and small chip manufacturers will have a level playing field with the giants in the industry. A development board like HiFive (Figure 2), which was recently funded on Crowd Supply [7], will be working with chips similar to those of Nvidia graphics cards. Nvidia's proprietary Falcon microcontrollers, which have been used for more than a decade, will be replaced in the next generation of products with RISC-V [8]. Similarly, Western Digital is partnering with SiFive to produce an estimated billion processing cores [9]. Not only is such an alliance of an industry giant with a small newcomer almost unheard of, but the result will be hardware that should be much easier for open hardware manufacturers to produce.

Figure 2: The HiFive development board is among the first to use a RISC-V chip.

Of course, some barriers will remain for open hardware. The custom space in the memory of RISC-V products will no doubt include proprietary code that must be reverse-engineered or replaced. Just as importantly, larger, long-established vendors will almost certainly have priority with manufacturers, forcing open hardware newcomers to wait at the back of the line behind those with high-volume orders. Still, if the RISC-V becomes as widely used as predicted, then many of the technical challenges will be removed. If that happens, the requirements for open hardware may shift from technical challenges to marketing and business development. In every sense of the word, RISC-V will have become a real game changer.